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Central processing unit
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#	Item
971	Alpha[removed]EV67 Microprocessor Hardware Reference Manual Order Number: DS–0028C–TE This manual is directly derived from the internal[removed]EV67 Specifications, Revision 1.5. You can access this hardware reference m Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:03:51 Computer engineering DEC Alpha Alpha 21264 PALcode CPU cache Processor register Instruction set Computer architecture Computer hardware Central processing unit
972	Removing Architectural Bottlenecks to the Scalability of Speculative Parallelization ´ Garzar´an, Lawrence Rauchwergery , and Josep Torrellas Milos Prvulovic, Mar´ıa Jesus University of Illinois at Urbana-Champaign Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-03-23 12:50:54 Computer memory Cache coherency Central processing unit CPU cache Cache Multi-core processor Speedup Automatic parallelization Memory hierarchy Computing Parallel computing Computer architecture
973	CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction Luis Ceze, Karin Strauss, James Tuck, Jose Renau† and Josep Torrellas University of Illinois at Urbana-Champaign {luisceze, kstrauss, jtuck, torrellas}@c Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2004-12-21 00:54:20 Central processing unit Runahead CPU cache Microprocessors Branch predictor Memory-level parallelism Microarchitecture Instruction window Hardware scout Computer architecture Computer hardware Computer engineering
974	The Stanford Hydra CMP Lance Hammond, Ben Hubbert, Michael Siu, Manohar Prabhu, Michael Chen, Maciek Kozyrczak, and Kunle Olukotun Computer Systems Laboratory Stanford University http://www-hydra.stanford.edu Add to Reading List Source URL: www-hydra.stanford.edu Language: English* - Date: 1999-11-05 21:09:40 Computer architecture CPU cache Cache Central processing unit Multi-core processor Parallel computing Direct memory access Harvard architecture Computer hardware Computing Computer memory
975	RelaxReplay: Record and Replay for Relaxed-Consistency Multiprocessors Nima Honarmand and Josep Torrellas University of Illinois at Urbana-Champaign {honarma1,torrella}@illinois.edu http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-01-10 19:23:01 Computing Parallel computing Instruction set CPU cache Microarchitecture Processor register Linearizability MIMD Computer architecture Computer hardware Central processing unit
976	Prototyping Architectural Support for Program Rollback Using FPGAs ∗ Radu Teodorescu and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign {teodores,torrellas}@cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-05-11 13:27:29 Computer engineering CPU cache Microarchitecture Speculative execution Processor register Application checkpointing Parallel computing Instruction set Multithreading Computer architecture Computer hardware Central processing unit
977	USING AN ADAPTIVE HPC RUNTIME SYSTEM TO RECONFIGURE THE CACHE HIERARCHY SC’14, Nov. 20, 2014 Ehsan Totoni, Josep Torrellas, Laxmikant V. Kale Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-12-19 19:14:48 Central processing unit Ø Slashed zero Numbers Information Computer memory Cache CPU cache
978	INSTITUTE OF PHYSICS PUBLISHING NANOTECHNOLOGY Nanotechnology[removed]–230 Add to Reading List Source URL: www.cellmatrix.com Language: English - Date: 2002-03-16 03:24:12 Integrated circuits Computer memory Central processing unit Cell Field-programmable gate array Arithmetic logic unit Computer Digital signal processor Shift register Electronic engineering Electronics Computer architecture
979	Illusionist: Transforming Lightweight Cores into Aggressive Cores on Demand Amin Ansari University of Illinois [removed] Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-01-25 16:46:06 Central processing unit Microprocessors Instruction set architectures Parallel computing DEC Alpha CPU cache Branch predictor Multithreading ARM architecture Computer architecture Computer hardware Computing
980	Technology in Higher Education Add to Reading List Source URL: www.cdtl.nus.edu.sg Language: English - Date: 2011-03-30 04:50:54 Microcontrollers Interrupts Embedded systems Instruction set Emulator ARM architecture Single-board microcontroller Computer Intel Computer architecture Instruction set architectures Central processing unit

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